The next AI bottleneck may be hiding under the heat spreader.
We keep discussing artificial intelligence as if intelligence were a property of a model. Count the parameters. Compare the benchmark. Admire the context window. Then quietly discover that the system is constrained by something less glamorous: where the weights live, how quickly they can move, and how many expensive memory stacks can be attached to the silicon.
The model is only one layer of the AI product.
A GPU-level study of large-batch language-model inference found that the workloads it examined could saturate memory bandwidth while leaving a substantial amount of arithmetic capacity unused. In those configurations, the limiting resource was not the ability to perform more calculations. It was the ability to feed the calculations with data. The paper reports that memory-bandwidth saturation was the primary bottleneck for the studied workloads, while also warning that the result depends on the model, hardware, batch size, precision, kernels, and serving regime.[1]
That is why accelerator specifications now read like memory catalogs. AMD lists 288 GB of HBM3E and 8 TB/s of peak memory bandwidth for its Instinct MI350X. Micron lists more than 1.2 TB/s per HBM3E placement, with 24 GB in an 8-high stack and 36 GB in a 12-high stack. These are vendor specifications, not promises about the throughput of a particular model. They still reveal what the hardware industry considers worth competing over: not only more computation, but more data kept close to it.[2] [3]
Memory capacity changes the shape of the problem. A model's weights must fit somewhere. So must the temporary state accumulated while it serves a long conversation or a large batch of requests. If the useful data fits in fast local memory, the accelerator can keep working near the core. If it does not, the system pays in traffic across slower tiers, additional devices, or interconnects. “How intelligent is the model?” becomes only one question. “Can the system keep the model fed?” becomes another.
The physical package now sits inside that question. TSMC said in its first-quarter 2025 earnings discussion that it was working to double CoWoS advanced-packaging capacity during 2025 because of customer demand. Micron said in September 2024 that its HBM supply was sold out for calendar years 2024 and 2025. Neither statement independently measures the entire market, but together they show that the path from a model design to a usable accelerator runs through a supply chain with its own hard limits.[4] [5]
This does not mean compute has stopped mattering. Some workloads remain compute-bound. Peak bandwidth is not achieved bandwidth. A company's “sold out” announcement describes its own allocation, not the whole global market. The mistake is to turn a layered engineering problem into a slogan about memory replacing compute.
The stronger conclusion is quieter: parameter count is no longer a sufficient proxy for deployability. Two models with similar capability can have radically different operational lives depending on precision, context length, cache behavior, batching, memory capacity, and the number of accelerators required to serve them. One may answer quickly on a single package. The other may become an expensive conversation between devices.
That changes what an AI product actually is. It is not a checkpoint floating above the hardware. It is a negotiated arrangement between algorithms, memory, packaging, cooling, power, software, and supply. The model proposes the intelligence. The physical stack decides how much of that proposal can exist at once.
We may remember the next phase of AI as a contest between model families. Underneath, it will also be a contest to make memory wider, closer, cheaper, and easier to manufacture. The winning system will not necessarily be the one with the largest model. It will be the one that can carry its intelligence without dropping half of it on the floor.
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